PXN20RM Datasheet, PDF (171/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Field
ERATE
EDEPTH
ERFD
Frequency Modulated Phase-Locked Loop (FMPLL)
Table 7-7. ESYNCR2 Field Descriptions (continued)
Description
Enhanced Modulation Rate. The ERATE bits control the rate of frequency modulation applied to the system
frequency. Table 7-8 shows the allowable modulation rates.
Note: The PLL modulation rate must be within the f_MOD specification (see the PXN20 Microcontroller Data
Sheet).
Enhanced Modulation Depth. The EDEPTH bit field controls the frequency modulation depth and enables the
frequency modulation. When programmed to a value other than 0x0, the frequency modulation is
automatically enabled. Table 7-9 shows are the programmable frequency deviations from the system
frequency. When the depth value is changed to a value other than 0x0, the calibration sequence is
reinitialized.
Enhanced Reduced Frequency Divider. The ERFD bits control a divider at the output of the PLL. The value
specified by the ERFD bits establish the divisor applied to the PLL frequency. The ERFD divides the output
clock by the quantity (ERFD + 1). Even-numbered ERFD settings, which would result in odd divide ratios, are
not allowed.
The decimal equivalent of the ERFD binary number is substituted into the equation from Table 7-11.
Note: The ERFD divides the output clock by the quantity (ERFD + 1). Even numbered ERFD settings, which
would result in odd divide ratios, are invalid and cause the PLL to produce an unpredictable output
clock. The PLL output clock must be within the f_PLL specification (see the PXN20 Microcontroller Data
Sheet).
Changing the ERFD bits does not affect the PLL, hence, no re-lock delay is incurred. Resulting changes in
clock frequency are synchronized to the next falling edge of the current system clock. These bits should be
written only when the lock bit (LOCK) is set, to avoid surpassing the allowable system operating frequency.
In PLL Off mode, the ERFD bits have no effect.
The available output divider ratios are given in Table 7-10.
Table 7-8. Programmable Modulation Rates
ERATE
00
01
10
11
Modulation Rate (Hz)
F_mod = F_extal/80
F_mod = F_extal/40
F_mod = F_extal/20
Invalid
Table 7-9. Programmable Modulation Depths
EDEPTH
000
001
010
011
100
101 – 111
Modulation Depth (% of F_sys)
0
0.25% – 0.5%
0.75% – 1.0%
1.25% – 1.5%
1.75% – 2.0%
Reserved
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
7-9