PXN20RM Datasheet, PDF(129/1376 Page) Freescale Semiconductor, Inc – PXN20 Microcontroller

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PXN20RM Datasheet, PDF (129/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

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System Clock Description

Table 5-2. Software-Controlled Clock Gating Support

Block Name

DSPI

ESCI

FlexCAN

EMIOS

CTU

PIT

I2C

NPC

Register Name

DSPI_MCR

Offset: Base + 0x0000

ESCIx_CR2

Offset: Base + 0x0004

CANx_MCR

Offset: Base + 0x0000

EMIOS_MCR

Offset: Base + 0x0000

CTUPCR

Offset: Base + 0x00CC

PITCTRL

Offset: Base + 0x0110

IBCR

Offset: Base + 0x0002

Nexus PCR[30]= MCKO_GT

Nexus PCR[29]= MCKO_EN==MDIS

Reg Index: 127

Bit Name

MDIS

MDIS

MDIS

MDIS

MDIS

MDIS

MDIS

MCKO_EN,

MCKO_GT

5.4.2 Halt Clock Gating

System clock gating is forced via the centralized halt mechanism. The SIU_HLT0 and SIU_HLT1 bits

corresponding to individual modules are configured to determine which modules are clock gated.

The SIU_HLT0 and SIU_HLT1 bits are used to drive the stop inputs to the modules. After the module

completes a clean shutdown, the module asserts the stop acknowledge handshake. The stop acknowledge

is visible in the SIU_HLTACK0 and SIU_HLTACK1 read-only register bits. The modules are individually

controlled and halted.

The halted module recovers when the HLT bit is cleared by software. After HLT is cleared, the deviceâs

logic re-enables the clocks to the modules and negates the stop signal after the required timing has been

met.

There is no hardware disable for the eDMA and FlexRay modules. Thus before setting the HLT bits for

these masters, software should take actions to prepare for the eDMA and FlexRay clocks to be stopped.

Then software sets the HLT bits for the eDMA and FlexRay to indicate to the clock logic that the clocks

to these modules can now be stopped.

When the Z0 and Z6 have executed WAIT instructions, then the clocks to the platform are also gated. The

platform logic includes the MPU, AXBS, AIPS, and ECSM. The INTC and SIU are not clock gated to

allow for an interrupt to be used to exit WAIT.

5.4.3 Core WAIT Clock Gating

Core clock gating is enabled via the CPU WAIT instruction.

Freescale Semiconductor

PXN20 Microcontroller Reference Manual, Rev. 1

5-11

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