PXN20RM Datasheet, PDF (601/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory.
The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data LSB first.
25.4.8 Ethernet Address Recognition
The FEC filters the received frames based on the type of destination address (DA)—individual (unicast),
group (multicast), or broadcast (all-ones group address). The difference between an individual address and
a group address is determined by the I/G bit (bit 40) in the destination address field. A flowchart for
address recognition on received frames is illustrated in the figures below.
Address recognition is accomplished through the use of the receive block and microcode running on the
microcontroller. The flowchart shown in Figure 25-26 illustrates the address recognition decisions made
by the receive block, while Figure 25-27 illustrates the decisions made by the microcontroller.
If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is deasserted, then the frame is
accepted unconditionally, as shown in Figure 25-26. Otherwise, if the DA is not a broadcast address, then
the microcontroller runs the address recognition subroutine, as shown in Figure 25-27.
If the DA is a group (multicast) address and flow control is disabled, then the microcontroller performs a
group hash table lookup using the 64-entry hash table programmed in GAUR and GALR. If a hash match
occurs, the receiver accepts the frame.
If flow control is enabled, the microcontroller does an exact address match check between the DA and the
designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines that the received frame is a
valid PAUSE frame, then the frame is rejected. Note the receiver detects a PAUSE frame with the DA field
set to either the designated PAUSE DA or to the unicast physical address.
If the DA is the individual (unicast) address, the microcontroller performs an individual exact match
comparison between the DA and 48-bit physical address that the user programs in the PALR and PAUR
registers. If an exact match occurs, the frame is accepted; otherwise, the microcontroller does an individual
hash table lookup using the 64-entry hash table programmed in registers, IAUR and IALR. In the case of
an individual hash match, the frame is accepted. Again, the receiver accepts or rejects the frame based on
PAUSE frame detection, shown in Figure 25-26.
If neither a hash match (group or individual), nor an exact match (group or individual) occur, then if
promiscuous mode is enabled (RCR[PROM] = 1), then the frame is accepted and the MISS bit in the
receive buffer descriptor is set; otherwise, the frame is rejected.
Similarly, if the DA is a broadcast address, broadcast reject (RCR[BC_REJ]) is asserted, and promiscuous
mode is enabled, then the frame is accepted and the MISS bit in the receive buffer descriptor is set;
otherwise, the frame is rejected.
In general, when a frame is rejected, it is flushed from the FIFO.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
25-35