PXN20RM Datasheet, PDF (522/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
24.1.2 Features
The eDMA has these major features:
• All data movement via dual-address transfers: read from source, write to destination
— Programmable source, destination addresses, transfer size, and support for enhanced
addressing modes
• Transfer control descriptor organized to support two-deep, nested transfer operations
— An inner data transfer loop defined by a minor byte transfer count
— An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
All three methods require one activation per execution of the minor loop
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are optionally enabled per channel and logically summed together to form
a single error interrupt.
• Support for scatter-gather DMA processing
• Support for complex data structures
• Support to cancel transfers via software or hardware
• Any channel can be programmed to be suspended by a higher priority channel’s activation, before
completion of a minor loop.
NOTE
eDMA channels 16–31 are not implemented on the PXN20.
24.1.3 Modes of Operation
There are two main operating modes of eDMA: normal mode and debug mode. These modes are briefly
described in this section.
24.1.3.1 Normal Mode
In normal mode, the eDMA is used to transfer data between a source and a destination. The source and
destination can be a memory block or an I/O block capable of operation with the eDMA.
24-2
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor