PXN20RM Datasheet, PDF (718/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
As indicated by Table 26-96, the application shall write to the message buffer data field and change the
commit bit CMT only if the transmit message buffer is in one of the states HDis, HDisLck, HLck,
HLckCCSa, HLckCCMa, or HLckCCMa. The application can change the state of a message buffer if it
issues the appropriate commands shown in Table 26-97. The state change is indicated through the
MBCCSRn[EDS] and MBCCSRn[LCKS] status bits.
If the transmit message buffer enters one of the states HDis, HDisLck, HLck, HLckCCSa, HLckCCMa, or
HLckCCMa the MBCCSRn[DVAL] flag is negated.
26.6.6.2.5 Message Transmission
As a result of the message buffer search described in Section 26.6.7, Individual Message Buffer Search,
the controller triggers the message available transition MA for as many as two transmit message buffers.
This changes the message buffer state from Idle to CCMa and the message buffers can be used for message
transmission in the next slot.
The controller transmits a message from a message buffer if both of the following two conditions are
fulfilled at the start of the transmission slot:
1. the message buffer is in the message available state CCMa
2. the message data are still valid (MBCCSRn[CMT] = 1)
In this case, the controller triggers the TX transition and changes the message buffer state to CCTx. A
transmit message buffer timing and state change diagram for message transmission is given in
Figure 26-121. In this example, the message buffer with message buffer number n is Idle at the start of the
search slot, matches the slot and cycle number of the next slot, and message buffer data are valid
(MBCCSRn[CMT] = 1).
Idle
MA
MT ^start
MT ^start
search[s+1]
TX
CCMa
CCTx
message transmit
slot s
slot s+1
Figure 26-121. Message Transmission Timing
SSS SU
CCSu ^Idle
MT ^start
slot s+2
MA
HU
TX
HLck
HLckCCMa
MT ^start
MT ^start
search[s+1]
slot s
CCMa
CCTx
message transmit
slot s+1
SSS
Idle
MT ^start
slot s+2
Figure 26-122. Message Transmission from HLck state with unlock
26-104
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor