PXN20RM Datasheet, PDF (1162/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Assert
System Reset
Process flow used to initialize z6 as “break request master”
and z0 as “break request slave”
This configuration causes the z0 to follow the z6 into debug mode
- Enable Nexus
- Select NPC PCR Register and
- Configure FPM, MCK_EN,
EVT_EN, and MCK fields.
- Access Nexus Dev Control Register 1
- Configure EOC Field (EVTO Control)
- Select OnCE DBCR0
- Set EDM Bit
- Select OnCE SNCR
(Shared Nexus Control Register)
- Configure NT bit field for Z6 Ownership
- Select OnCE Control Register (OCR)
- Set DR bit (request debug mode right
out of reset).
NPC
Z0
Z6
Z0, Z6 Multi
- Select OnCE Control Register (OCR)
- Set DR bit (request debug mode right
out of reset).
Negate
System Reset
Figure 36-4. Flow for Enabling e200z0 to put the e200z6 into Debug Mode
36-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor