PXN20RM Datasheet, PDF (181/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
CAUTION
When running in an unlocked state, the clocks generated by the PLL are not
guaranteed stable and may exceed the maximum specified operating
frequency of the device. The RFD should always be used as described in
Section 7.4.3.3.5, Programming System Clock Frequency, to insulate the
system from any potential frequency overshoot of the PLL clocks.
7.5.2 PLL Loss-of-Lock Reset
By programming the LOLRE bit in the ESYNCR2, the PLL can assert reset when a loss-of-lock condition
occurs. Because the LOCK and LOCKS bits in the SYNSR are re-initialized after reset, the SIU reset status
register described in Chapter 8, System Integration Unit (SIU), must be read to determine a loss-of-lock
condition occurred.
In PLL Off mode, the PLL cannot lock; therefore a loss-of-lock condition cannot occur and LOLRE has
no effect.
7.5.3 PLL Loss-of-Clock Reset
When a loss-of-clock condition is recognized, RESET is asserted if the LOCRE bit in the SYNCR is set.
The LOCF and LOC bits in the SYNSR are cleared after reset, therefore, the LOC bit must be read in the
SIU_RSR to determine that a loss-of-clock condition occurred. LOCRE has no effect in PLL Off mode.
7.6 Interrupts
This section describes the interrupt requests that the PLL can generate.
7.6.1 Loss-of-Lock Interrupt Request
By setting the LOLIRQ bit in the ESYNCR2, the PLL can request an interrupt when a loss-of-lock
condition occurs.
In PLL Off mode, the PLL cannot lock; therefore a loss-of-lock condition cannot occur and the LOLIRQ
has no effect.
7.6.2 Loss-of-Clock Interrupt Request
When a loss-of-clock condition is recognized, the PLL requests an interrupt if the LOCIRQ bit in the
SYNCR is set. The LOCIRQ bit has no effect in PLL Off mode or if LOCEN is equal to 0.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
7-19