PXN20RM Datasheet, PDF (967/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
DSPI_CTARn[BR]) to produce SCK with the possibility of halving the scaler division. The DBR, PBR,
and BR fields in the DSPI_CTARn registers select the frequency of SCK using the following formula:
SCK baud rate
=
-----------------------f-S-----Y----S-------------------------
PBRPrescalerValue

-----------1-----+-----D-----B----R--------------
BRScalerValue
Eqn. 30-5
Table 30-26 shows an example of a computed baud rate.
Table 30-26. Baud Rate Computation Example
f_SYS
PBR
66 MHz
20 MHz
0b00
0b00
Prescaler
Value
2
2
BR
0b0000
0b0000
Scaler
Value
2
2
DBR
Value
0
1
Baud Rate
16.67 Mbit/s
10 Mbit/s
30.4.7.2 PCS to SCK Delay (t_CSC)
The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge. See
Figure 30-29 for an illustration of the PCS to SCK delay. The PCSSCK and CSSCK fields in the
DSPI_CTARn registers select the PCS to SCK delay, and the relationship is expressed by the following
formula:
t_CSC =
1 _{ PCSSCK  CSSCK}
f_SYS
Eqn. 30-6
Table 30-27 shows an example of the computed PCS to SCK delay.
Table 30-27. PCS to SCK Delay Computation Example
PCSSCK
0b01
Prescaler
Value
3
CSSCK
0b0100
Scaler
Value
32
f_SYS
100 MHz
PCS to SCK Delay
0.96 µs
30.4.7.3 After SCK Delay (t_ASC)
The after SCK delay is the length of time between the last edge of SCK and the negation of PCS. See
Figure 30-29 and Figure 30-30 for illustrations of the after SCK delay. The PASC and ASC fields in the
DSPI_CTARn registers select the after SCK delay. The relationship between these variables is given in the
following formula:
t_ASC =
1
 PASC
f_SYS
 ASC
Table 30-28 shows an example of the computed after SCK delay.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
30-41