PXN20RM Datasheet, PDF (552/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
eDMA
SRAM
Transfer control descriptor
(TCD)
Slave write address
Slave write data
SRAM
TCD0
eDMA engine
Bus read data
Data path
Bus write data
Bus address
Program model/
channel arbitration
Address
path
Control
TCDn-1*
Slave read data
*n = 32 channels
eDMA interrupt request eDMA peripheral request
eDMA done handshake
Figure 24-19. eDMA Operation, Part 1
In the second part of the basic data flow as shown in Figure 24-20, the modules associated with the data
transfer (address path, data path, and control) sequence through the required source reads and destination
writes to perform the actual data movement. The source reads are initiated and the fetched data is
temporarily stored in the data path module until it is gated onto the system bus during the destination write.
This source read/destination write processing continues until the inner minor byte count has been
transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer.
24-32
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor