PXN20RM Datasheet, PDF (1021/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
• During the reception of the STOP bit of frame n the host reads the SCI
Data Registers, and clears the RDRF flag
In this case the RDRF flag is erroneously set again by the controller instead
of the OR flag. Thus, the host reads the data of frame n-1 a second time, and
the data of frame n is lost.
The application should ensure that the data of the foregoing frame is read
out from the SCI Data Registers before the last data bit of the actual frame
is received.
31.4.5.2.5 Parity Generation
The eSCI module generates the parity bit in transmitted data frame when the parity enable bit PE in the
eSCI Control Register 1 (eSCI_CR1) is set. The parity type bit PT in the eSCI Control Register 1
(eSCI_CR1) defines whether the odd or even parity is generated.
31.4.5.2.6 Preamble Transmission
The transmission of a preamble is started when the transmitter is in ready state, the internal iPRE bit, which
is not visible to the application, is set, and the SBK in the eSCI Control Register 1 (eSCI_CR1) is clear.
After the transmission of the stop bit and if the application has not disabled the transmitter, the transmitter
returns to the ready state via the done transition. If no frame or character transmit request is pending, the
transfer complete flag TC in the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set.
If the application has disabled the transmitter while the preamble is transmitted and if the stop bit has been
transmitted, the transmitter goes into the idle state via the halt transition. The transfer complete flag TC in
the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set and the internal commit bit iCMT is
cleared.
31.4.5.2.7 Break Character Transmission
The transmission of a break character is started when the transmitter is in ready state and the send break
character bit SBK in the eSCI Control Register 1 (eSCI_CR1) is set. After the transmission of the break
character and if the application has not disabled the transmitter, the transmitter returns to the ready state
via the done transition and restarts the transmission. As long as SBK bit remains set, the transmitter
continues to send break characters.
When the application has cleared the SBK bit or has disabled the transmitter, the transmitter continues to
transmit the current break character. After it has finished the transmission of this break character it
transmits a stop bit. The stop bit at the end of a break character sequence guarantees the recognition of the
start bit of the next data frame.
After the transmission of the stop bit and if the application has not disabled the transmitter, the transmitter
returns to the ready state via the done transition. If no frame or character transmit request is pending, the
transfer complete flag TC in the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set.
If the application has disabled the transmitter while the break character is transmitted and if the stop bit
has been transmitted, the transmitter goes into the idle state via the halt transition. The transfer complete
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
31-31