|
PXN20RM Datasheet, PDF (929/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller | |||
|
◁ |
Deserial â Serial Peripheral Interface (DSPI)
â Parameterized number of transfer attribute registers (from two to eight)
â Serial clock with programmable polarity and phase
â Various programmable delays
â Programmable serial frame size of 4 to 32 bits, expandable by software control
â Continuously held chip select capability
⢠Six peripheral chip selects, expandable to 32 with external demultiplexer
⢠Deglitching support for as many as 128 peripheral chip select with external demultiplexer
⢠DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
â TX FIFO is not full (TFFF)
â RX FIFO is not empty (RFDF)
⢠Six Interrupt conditions:
â End of queue reached (EOQF)
â TX FIFO is not full (TFFF)
â Transfer of current frame complete (TCF)
â Attempt to transmit with an empty Transmit FIFO (TFUF)
â RX FIFO is not empty (RFDF)
â Frame received while Receive FIFO is full (RFOF)
⢠Modified SPI transfer formats for communication with slower peripheral devices
⢠Module disable mode supported via MDIS bits in the DSPI block
⢠Halt mode supported via HLT bits in the SIU block
The DSPI also supports pin reduction through serialization and deserialization.
⢠Two sources of serialized data:
â DSPI memory-mapped register
â Parallel Input signals
⢠Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register
⢠Transfer initiation conditions:
â Continuous
â Change in data
⢠Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
⢠Continuous serial communications clock
⢠Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the
Micro Second Bus downstream frame format.
30.1.3 DSPI Configurations
The DSPI block has three distinct serial transmission configurations; SPI, DSI and CSI.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
30-3
|
▷ |