PXN20RM Datasheet, PDF (1061/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Inter-Integrated Circuit Bus Controller Module (I²C)
interrupt function is enabled during initialization by setting the IBIE bit. The IBIF (interrupt flag) can be
cleared by writing 1 (in the interrupt service routine, if interrupts are used).
The TCF bit is cleared to indicate data transfer in progress by reading the IBDR data register in receive
mode or writing the IBDR in transmit mode. The TCF bit must not be used as a data transfer complete flag
because the flag timing depends on a number of factors including the I²C bus frequency. This bit may not
conclusively provide an indication of a transfer complete situation. Transfer complete situations must be
detected using the IBIF flag
Software may service the I²C I/O in the main program by monitoring the IBIF bit if the interrupt function
is disabled. Polling should monitor the IBIF bit rather than the TCF bit because their operation is different
when arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit mode, i.e., the
address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR, then the TX bit
should be toggled at this stage.
During slave mode address cycles (IAAS = 1) the SRW bit in the status register is read to determine the
direction of the subsequent transfer and the TX bit is programmed accordingly. For slave mode data cycles
(IAAS = 0) the SRW bit is not valid. The TX bit in the control register should be read to determine the
direction of the current transfer.
The following is an example software sequence for master transmitter in the interrupt routine.
clear bit 6, IBSR
if (bit 2, IBCR ==0)
slave_mode()
if (bit 3, IBCR ==0))
receive_mode()
if (bit 7, IBSR == 1)
end();
else
IBDR = data_to_transmit
// Clear the IBIF flag
// run slave mode routine
// run receive_mode routine
// if NO ACK
// end transmission
// transmit next byte of data
32.5.1.4 Generation of STOP
A data transfer ends with a STOP signal generated by the master device. A master transmitter can simply
generate a STOP signal after all the data has been transmitted. The following example shows how a stop
condition is generated by a master transmitter.
if (tx_count == 0) or
// check to see if all data bytes have been transmitted
(bit 7, IBSR == 1) { // or if no ACK generated
clear bit 2, IBCR // generate stop condition
}
else {
IBDR = data_to_transmit // write byte of data to DATA register
tx_count --
// decrement counter
}
// return from interrupt
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data. This can be done by setting the transmit acknowledge bit (TXAK)
before reading the second last byte of data. Before reading the last byte of data, a STOP signal must first
be generated. The following example shows how a STOP signal is generated by a master receiver.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
32-17