PXN20RM Datasheet, PDF (1118/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
34.3.2.34 Power Down Exit Delay Register (PDEDR)
The PDEDR register specifies the delay between the power-down reset and the start of the next conversion.
Address: ADC_BASE + 0x00C8
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
0
0
0
0
0
0
0
W
PDED
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-35. Power Down Exit Delay Register (PDEDR)
Table 34-37. PDEDR Field Descriptions
Field
PDED
Description
The delay between the power down bit MCR[PWDN] reset and the start of the next conversion.
34.3.2.35 Precision Channel n Data Register (PRECDATAREGn)
The PRECDATAREGn registers provide conversion results for the group 0 channel (channels 0–31) data
registers. Each data register gives also some information regarding the corresponding result. One
PRECDATAREGn register is provided for each channel.
Address: See Table 34-1.
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
VALID OVERW RESULT
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R
0
W
Reset 0
Field
VALID
OVERW
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
CDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-36. Precision Channel n Data Register (PRECDATAREGn)
0
0
Table 34-38. PRECDATAREGn Field Descriptions
Description
Used to notify when the data is valid (a new value has been written). It is automatically cleared when data is
read.
Overwrite data. Used to notify when a conversion data is overwritten by a newer result.The new data is written
or discarded according to the OWREN bit of MCR register.
34-38
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor