PXN20RM Datasheet, PDF (1092/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
Address: ADC_BASE + 0x0010
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
0
0
0
0
0
0
0
0
OFF
CANC
OVR
EOFF
SET
EO
CTU
JEOC JECH EOC
ECH
W
w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-4. Interrupt Status Register (ISR)
Table 34-4. ISR Field Descriptions
Field
Description
OFFCANCOVR Offset Cancellation Phase Over interrupt (OFFCANCOVR) flag. When the ADC generates the offset_ok_i to
high indication then the offset cancellation phase programmed by the user is over and the offset coefficient is
written into the offset register. When this bit is set, an OFFCANCOVR interrupt has occurred.
EOFFSET
Error in Offset Refresh interrupt (EOFFSET) flag. This interrupt is generated during the offset cancellation
phase in case the offset_measure_ok_i pulse is not received. When this bit is set, an EOFFSET interrupt has
occurred.
EOCTU
End of CTU Conversion interrupt (EOCTU) flag. It is the interrupt of the digital end of conversion for the CTU
channel; active when set. When this bit is set, an EOCTU interrupt has occurred.
JEOC
End of Injected Channel Conversion interrupt (JEOC) flag. It is the interrupt of the digital end of conversion for
the injected channel; active when set. When this bit is set, a JEOC interrupt has occurred.
JECH
End of Injected Chain Conversion interrupt (JECH) flag. It is the interrupt of the digital end of chain conversion
for the injected channel; active when set. When this bit is set, a JECH interrupt has occurred.
EOC
End of Channel Conversion interrupt (EOC) flag. It is the interrupt of the digital end of conversion. When this
bit is set, an EOC interrupt has occurred.
ECH
End of Chain Conversion interrupt (ECH) flag. It is the interrupt of the digital end of chain conversion. When
this bit is set, an ECH interrupt has occurred.
34.3.2.4 Channel Pending Register 0 (CEOCFR0)
Three Channel Interrupt Pending Registers are provided to signal which of the 96 channels’ measures have
been completed. These are COCFR[0:2]. CEOCFR0 is the End of Conversion Pending Interrupt register
for group 0 channels (channels 0–31).
34-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor