PXN20RM Datasheet, PDF (1001/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Table 31-6. eSCI_DR Field Descriptions
Field
Description
RN
TN
ERR
RD[11:8]
RD7
TD7
RD[6:0]
TD[6:0]
Received Most Significant Bit. The semantic of this bit depends on the frame format selected by eSCI_CR3[M2],
eSCI_CR1[M], and eSCI_CR1[PE].
[M2 = 0,M = 1,PE = 0]: value of received data bit 8 or address bit.
[M2 = 0,M = 1,PE = 1]: value of received parity bit if eSCI_CR2[PMSK] = 0, 0 otherwise.
[M2 = 1,M = 0,PE = 1]: value of received parity bit if eSCI_CR2[PMSK] = 0, 0 otherwise.
[M2 = 1,M = 1,PE = 1]: value of received parity bit if eSCI_CR2[PMSK] = 0, 0 otherwise.
It is 0 for all other frame formats.
Transmit Most Significant Bit. The semantic of this bit depends on the frame format selected by eSCI_CR3[M2],
eSCI_CR1[M], and eSCI_CR1[PE].
[M2 = 0,M = 1,PE = 0]: value to be transmitted as data bit 8 or address bit.
It is not used for all other frame formats.
Receive Error Bit. This bit indicates the occurrence of the errors selected by the Control Register 3 (eSCI_CR3)
during the reception of the frame presented in SCI Data Register (eSCI_SDR). In case of an overrun error for
subsequent frames this bit is set too.
0 None of the selected errors occured.
1 At least one of the selected errors occured.
Received Data. The semantic of this field depends on the frame format selected by eSCI_CR3[M2] and
eSCI_CR1[M].
[M2 = 1,M = 1]: value of the received data bits 11:8. (Rn = BITn).
It is all 0 for all other frame formats.
Received Bit 7. The semantic of this bit depends on the format selected by eSCI_CR3[M2], eSCI_CR1[M], and
eSCI_CR1[PE].
[M2 = 0,M = 0,PE = 0]: value of received bit 7 or ADDR bit.
[M2 = 0,M = 0,PE = 1]: value of received parity bit if eSCI_CR2[PMSK] = 0, 0 otherwise.
For all other frame formats it is the value of received bit 7.
Transmit Bit 7. The semantic of this bit depends on the format selected by eSCI_CR3[M2], eSCI_CR1[M], and
eSCI_CR1[PE].
[M2 = 0,M = 0,PE = 0]: value of transmit bit 7 or ADDR bit.
[M2 = 0,M = 0,PE = 1]: not used. Parity bit is generated internally before transmission.
For all other frame formats it is the value of transmit bit 7.
Received bits 6 to 0. Value of received BITn is shown in bit RDn
Transmit bits 6 to 0. Value of bit TDn is transmitted in BITn.
31.3.2.5 eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1)
This register provides interrupt flags that indicate the occurrence of module events. The related interrupt
enable bits are located in Control Register 1 (eSCI_CR1) and Control Register 2 (eSCI_CR2).
Offset: ESCI_BASE + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R TDRE TC RDRF IDLE OR NF FE PF 0
0
0 BERR 0
0 TACT RACT
W w1c w1c w1c w1c w1c w1c w1c w1c
w1c
Reset 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 31-6. eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
31-11