PXN20RM Datasheet, PDF (150/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Clocks, Reset, and Power (CRP)
interrupt when the device wakes up. Each external wake-up has individual wakeup flag and interrupt
enable and are grouped together into one interrupt vector. Refer to Chapter 3, Signal Description, for
details on the allocation of pins to the Wake-up lines.
In order to minimize spurious wake-up as a result of noise, fixed duration input filters are applied to every
wake-up pin.These filters are based on either the 128 kHz or 16 MHz clock sources and use 2 clock cycles
to synchronize the input wake-up signal.
6.3.3 Low-Power Mode Entry
The sequence to enter the low-power sleep mode is for the user to disable the DMA, MLB, FEC, and
FlexRay masters. Then halt all modules via the SIU_HLT registers. The system clock source should be set
to the 16 MHz IRC prior to disabling the PLL or powering down the 4 – 40 MHz XTAL. The PLL should
then be disabled since it does not clock any logic in sleep mode.
The main external oscillator (4 – 40 MHz XTAL) can be optionally powered down in sleep mode by
clearing the EN40MOSC bit in the CRP_CLKSRC register. If EN40MOSC is enabled during Sleep, and
EN40MOSC is 0, then the 4 – 40 MHz OSC can not be used as a clock source during sleep, but is still
actively driving the external crystal which may support the full 4 – 40 MHz frequency range. If
EN40MOSC is enabled during Sleep, and EN40MOSC is 1, then the 4 – 40 MHz XTAL may be used as
a clock source for the RTC/API during sleep, but the external crystal frequency is limited to less than or
equal to 8 MHz.
If the 4 – 40 MHz XTAL is powered down for sleep mode, the crystal oscillator must restart on the exit
from sleep mode. If the 4 – 40 MHz XTAL powered down option is chosen, the user must be sure to first
disable any logic that is being clocked directly by the 4 – 40 MHz XTAL to prevent glitches.
All program and erase operations on the flash array need to be completed before entering sleep mode.
Prior to entry into sleep mode, the ADC halt bit must be set or the ADC must be disabled. When exiting
sleep mode, the required recovery time must elapse before the ADC can be enabled or the ADC halt bit is
cleared. The recovery time allows the ADC circuits to stabilize. See the PXN20 Microcontroller Data
Sheet for recovery times.
Sleep mode selection is done by setting the SLEEP bit in the CRP_PSCR register. With this bit set, each
active core should individually execute the WAIT instruction to enter sleep mode. If only one core is
active, and one is held in reset by the user, then executing the WAIT instruction on the active core initiates
entry into the low-power mode. At this point, the CRP takes over operation of the device until a wakeup
event occurs.
6.3.3.1 CRP Clock Selection
In sleep mode, the CRP control logic is clocked by the 16 MHz IRC. The RTC/API can be clocked by the
128 kHz_IRC, the 32 kHz_XTAL, the 16 MHz IRC, or the 4 – 40 MHz XTAL (restricted to less than or
equal to 8 MHz). The pin wakeup logic can be clocked by either the 128 kHz IRC or the 16 MHz IRC.
These clock source selections must be made prior to executing both WAIT instructions to the cores.
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor