PXN20RM Datasheet, PDF (1214/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
3. Repeat step 3 in Section 36.6.10.6.1, Single Write Access until the internal CNT value is zero (0).
When this occurs, the DV bit within the RWCS is cleared to indicate the end of the block write
access.
36.6.10.6.3 Block Write Access (Burst Mode)
1. For a burst block write access, follow Steps 1 and 2 outlined in Section 36.6.10.6.1, Single Write
Access to initialize the registers, using a value of four (double-words) for the CNT field and a
RWCS[SZ] field indicating 64-bit access.
2. Initialize the burst data buffer (read/write access data register) through the access method outlined
in Section 36.6.9, Nexus3+ Register Access via JTAG / OnCE, using the Nexus register Index of
0xA (see Table 36-19).
3. Repeat step 2 until all double-word values are written to the buffer.
NOTE
The data values must be shifted in 32-bits at a time LSB first (that is,
double-word write = two word writes to the RWD).
4. The Nexus module then arbitrates for the system bus and transfer the burst data values from the
data buffer to the system bus beginning from the memory mapped address in the read/write access
address register (RWA). For each access within the burst, the address from the RWA register is
incremented to the next double-word size (specified in the SZ field) modulo the length of the burst,
and the number from the CNT field is decremented.
5. When the entire burst transfer has completed without error (ERR = 0), the DV bit within the RWCS
is cleared to indicate the end of the block write access.
NOTE
The actual RWA value as well as the CNT field within the RWCS are not
changed when executing a block write access (burst or non-burst). The
original values can be read by the external development tool at any time.
36.6.10.6.4 Single Read Access
1. Initialize the read/write access address register (RWA) through the access method outlined in
Section 36.6.9, Nexus3+ Register Access via JTAG / OnCE, using the Nexus register index of 0x9
(see Table 36-19). Configure as follows:
– Read Address  0xnnnn_nnnn (read address)
2. Initialize the read/write access control/status register (RWCS) through the access method outlined
in Section 36.6.9, Nexus3+ Register Access via JTAG / OnCE, using the Nexus register index of
0x7 (see Table 36-19). Configure the bits as follows:
– Access Control RWCS[AC]  0b1 (to indicate start access)
– Map Select RWCS[MAP]  0b000 (primary memory map)
– Access Priority RWCS[PR]  0b00 (lowest priority)
– Read/Write RWCS[RW]  0b0 (read access)
– Word Size RWCS[SZ]  0b0xx (32-bit, 16-bit, 8-bit)
36-64
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor