PXN20RM Datasheet, PDF (687/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
26.5.2.67.30 Protocol Configuration Register 29 (PCR29)
Base + 0x00DA
0
1
2
3
4
5
6
7
8
9
10
11
12
R _{extern_offset_}
W
correction
minislots_max
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-97. Protocol Configuration Register 29 (PCR29)
26.5.2.67.31 Protocol Configuration Register 30 (PCR30)
Write: POC:config
13
14
15
0
0
0
Base + 0x00DC
0
1
R0
0
W
Reset 0
0
Write: POC:config
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
sync_node_max
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-98. Protocol Configuration Register 30 (PCR30)
26.5.2.68 Message Buffer Configuration, Control, Status Registers (MBCCSRn)
Base + 0x0100 (MBCCSR0)
Base + 0x0108 (MBCCSR1)
...
Write: MCM, MBT, MTD: POC:config or MB_DIS
CMT: MB_LCK or MB_DIS
EDT, LCKT, MBIE, MBIF: Normal Mode
Base + 0x04F8 (MBCCSR127)
Additional Reset: CMT, DUP, DVAL, MBIF: Message Buffer Disable
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
CMT 0
0
0
0
0 DUP DVAL EDS LCKS MBIF
MCM MBT MTD
MBIE
W
rwm EDT LCKT
w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-99. Message Buffer Configuration, Control, Status Registers (MBCCSRn)
The content of these registers comprises message buffer configuration data, message buffer control data,
message buffer status information, and message buffer interrupt flags. A detailed description of all flags
can be found in Section 26.6.6, Individual Message Buffer Functional Description.
If the application writes 1 to the EDT bit, no write access to the other register bits is performed.
If the application writes 0 to the EDT bit and 1 to the LCKT bit, no write access to the other bits is
performed.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
26-73