PXN20RM Datasheet, PDF (232/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Offset: SIU_BASE + 0x0C10
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PJ0:PJ15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PK0:PK10
W
0
0
0
0
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-39. Parallel GPIO Pin Data Output Register 4 (SIU_PGPDO4)
8.3.2.32 Parallel GPIO Pin Data Input Register 0 (SIU_PGPDI0)
Reads to the SIU_PGPDI0 register provide the parallel GPIO pin data input for PA[0:15] and PB[0:15].
Writes have no effect.
Reads of this register are coherent with the registers SIU_GPDI0_3, SIU_GPDI4_7, SIU_GPDI8_11,
SIU_GPDI12_15, SIU_GPDI16_19, SIU_GPDI20_23, SIU_GPDI24_27, and SIU_GPDI28_31.
Offset: SIU_BASE + 0x0C40
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PA0:PA15
W
Reset U U U U U U U U U U U U U U U U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PB0:PB15
W
Reset U U U U U U U U U U U U U U U U
Figure 8-40. Parallel GPIO Pin Data Input Register 0 (SIU_PGPDI0)
8.3.2.33 Parallel GPIO Pin Data Input Register 1 (SIU_PGPDI1)
Reads to the SIU_PGPDI1 register provide the parallel GPIO pin data input for PC0:PC15 and PD0:PD15.
Writes have no effect.
Reads of this register are coherent with the registers SIU_GPDI32_35, SIU_GPDI36_39,
SIU_GPDI40_43, SIU_GPDI44_47, SIU_GPDI48_51, SIU_GPDI52_55, SIU_GPDI56_59, and
SIU_GPDI60_63.
8-50
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor