PXN20RM Datasheet, PDF (1074/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Cross Triggering Unit (CTU)
Offset: CTU_BASE + 0x0020 (CTU_CVR0)
0x0024 (CTU_CVR1)
0x0028 (CTU_CVR2)
0x002C (CTU_CVR3)
0
1
2
3
4
5
6
7
8
9
R
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
Access: User read/write
10 11 12 13 14 15
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
0
0
0
0
0
0
CV[8:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 33-5. Current Value Register (CTU_CVRn)
Table 33-6. CTU_CVRm Register Field Descriptions
Bit
Description
CV[8:0] Current Value. These bits contain the current value of the counter. The counter starts counting from the start value
loaded from corresponding start value register down to 0x000 as soon as a valid input event is detected.
33.4.1.4 Event Configuration Register (CTU_EVTCFGRn)
Event configuration registers 0 – 31 are associated with eMIOS channels 0 – 31. Event configuration
register 32 is associated with PIT3.
Offset: CTU_BASE + 0x0030–0x00B0
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
TM
W
COUNT_
GROUP
0
DELAY_INDEX
CLR_
FLAG
0
CHANNEL_VALUE
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 33-7. Event Configuration Register (CTU_EVTCFGRn)
Table 33-8. CTU_EVTCFGRn Register Field Descriptions
Bit
TM
Trigger Mask.
0 Trigger masked.
1 Trigger enabled.
Description
33-6
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor