PXN20RM Datasheet, PDF (391/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Bits
9
10
11
12
13
14
15
16–20
21
22
23
Name
AWDD
WAM
CWM
DPB
DSB
DSTRM
CPE
—
CUL
CLO
CLFC
e200z6 Core (Z6)
Table 13-10. L1CSR0 Field Descriptions (continued)
Description
Additional ways data disable.
0 Additional ways beyond 0–3 are available for replacement by data miss line fills.
1 Additional ways beyond 0–3 are not available for replacement by data miss line fills.
For the 32KB 8-way cache, ways 4–7 are considered additional ways. When configured as a
4-way cache, this bit is ignored.
Way access mode
0 Disable way access is checked not enabled for replacement on an access type are still
checked for a cache hit for accesses of that type but are not replaced by an access miss of
that type.
1 Ways not enabled for replacement on a particular access type (instruction vs. data) via the
AWID, WID, AWDD, and WDD fields are disabled and no lookup is performed for accesses
of that type. Selecting WAM = 1 helps minimize power consumption.
Software must ensure that the instruction to data coherency is maintained when using the
power-saving feature of the WAM control. Cache must be invalidated prior to changing the
value of this bit. Use of a dcbf followed by an icbi, msync, isync for modified lines which can be
executed is required to maintain proper operation.
Cache write mode
0 Cache operates in writethrough mode
1 Cache operates in copyback mode
When set to writethrough mode, the “W” page attribute from an optional MMU is ignored and
all writes are treated as writethrough required. When set, write accesses are performed in
copyback mode unless the “W” page attribute from an optional MMU is set.
Disable push buffer
0 Push buffer enabled
1 Push buffer disabled
Disable store buffer
0 store buffer enabled
1 store buffer disabled
Disable streaming
0 streaming is enabled
1 streaming is disabled
Cache parity enable
0 parity checking is disabled
1 parity checking is enabled
Reserved
Cache unable to lock. Indicates a lock set instruction was not effective in locking a cache line.
This bit is set by hardware on an “unable to lock” condition (other than lock overflows), and
remains set until cleared by software writing 0 to this bit location.
Cache lock overflow Indicates a lock overflow (overlocking) condition occurred. This bit is set
by hardware on an “overlocking” condition, and remains set until cleared by software writing 0
to this bit location.
Cache lock bits flash clear. When written to a 1, a cache lock bits flash clear operation is
initiated by hardware. After this is complete, this bit is reset to 0. Writing a 1 while a flash clear
operation is in progress results in an undefined operation. Writing a 0 to this bit while a flash
clear operation is in progress is ignored. Cache lock bits flash clear operations require
approximately cycles to complete. Clearing occurs regardless of the enable (CE) value.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
13-27