PXN20RM Datasheet, PDF (390/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z6 Core (Z6)
The correct sequence necessary to change the value of LSCSR0 is as follows:
1. msync
2. isync
3. mtspr L1CSR0
0
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1010; Read/Write; Reset - 0x0
Figure 13-16. L1 Cache Control and Status Register 0 (L1CSR0)
The L1CSR0 bits are described in Table 13-10.
Table 13-10. L1CSR0 Field Descriptions
Bits
Name
Description
Way instruction disable.
0 The corresponding way is available for replacement by instruction miss line fills.
1 The corresponding way is not available for replacement by instruction miss line fills.
0:3
WID
Bit 0 corresponds to way 0.
Bit 1 corresponds to way 1.
Bit 2 corresponds to way 2.
Bit 3 corresponds to way 3.
The WID and WDD bits can be used for locking ways of the cache, and also are used in
determining the replacement policy of the cache.
Way data disable.
0 The corresponding way is available for replacement by data miss line fills.
1 The corresponding way is not available for replacement by data miss line fills.
4:7
WDD
Bit 4 corresponds to way 0.
Bit 5 corresponds to way 1.
Bit 6 corresponds to way 2.
Bit 7 corresponds to way 3.
The WID and WDD bits can be used for locking ways of the cache, and also are used in
determining the replacement policy of the cache.
Additional ways instruction disable.
0 Additional ways beyond 0–3 are available for replacement by instruction miss line fills.
8
AWID
1 Additional ways beyond 0–3 are not available for replacement by instruction miss line fills.
For the 32KB 8-way cache, ways 4–7 are considered additional ways. When configured as a
4-way cache, this bit is ignored.
13-26
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor