PXN20RM Datasheet, PDF (364/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
per 64 bit ECC segment between erases. Erase of the shadow row is done similarly as an array erase. See
section Section 12.4.1.4, Flash Erase, for more information.
12.4.4 Flash Sleep Mode
Flash sleep mode is entered by setting the FDIS bit in the CPR_SOCSC register. See Section 6.2.2.12, SoC
Status and Control Register (CRP_SOCSC), for more information. Once sleep mode is requested, the flash
module turns off most current sources, although logic/charge pumps to enable quick recovery to read are
enabled for faster wake up time than disable mode.
When in sleep mode, register access is prevented. FC accesses are also prevented until sleep mode is
exited. FC reads and writes may occur as soon as sleep mode is exited.
The flash module returns to its pre-sleep state when enabled in all cases unless in the process of executing
a program or erase high voltage operation at the time of sleep. If the flash module is put to sleep during a
program or erase high voltage operation, the appropriate suspend bit is set to a 1. The user may resume the
program or erase operation at the time the module is enabled by clearing the appropriate suspend bit. EHV
must be high for the module to resume operation. If both the ESUS and PSUS bits are set to a 1 the user
must clear PSUS to resume the program. The erase may be resumed after the program ends.
12.4.5 Flash Reset
A reset is the highest priority operation for the flash and terminates all other operations.
The flash uses reset to initialize register and status bits to their default reset values. If the flash is executing
a program or erase operation and a reset is issued, the operation is aborted and the flash disables the high
voltage logic without damage to the high-voltage circuits. Reset aborts all operations and forces the flash
into user mode ready to receive accesses.
After reset is negated, register accesses can be performed, although it should be noted that registers that
require updating from shadow information, or other inputs, cannot read updated until flash exits reset.
12.4.6 DMA Requests
The flash has no DMA requests.
12.4.7 Interrupt Requests
The flash has no interrupt requests.
12-38
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor