PXN20RM Datasheet, PDF (976/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
CONT bit in the SPI command. Continuous selection is enabled for the DSI configuration by setting the
DCONT bit in the DSPI_DSICR. The behavior of the PCS signals in the two configurations is identical,
so only SPI configuration is described.
When the CONT bit = 0, the DSPI drives the asserted chip select signals to their idle states in between
frames. The idle states of the chip select signals are selected by the PCSIS field in the DSPI_MCR.
Figure 30-33 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 0.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master SOUT
Master SIN
PCSx
t_CSC
t_ASC
t_DT
t_CSC = PCS to SCK delay.
t_CSC
t_ASC = After SCK delay.
t_DT = Delay after transfer (minimum CS negation time).
Figure 30-33. Example of Non-Continuous Format (CPHA = 1, CONT = 0)
When the CONT bit = 1and the PCS signal for the next transfer is the same as for the current transfer, the
PCS signal remains asserted for the duration of the two transfers. The delay between transfers (t_DT) is not
inserted between the transfers. Figure 30-34 shows the timing diagram for two 4-bit transfers with
CPHA = 1 and CONT = 1.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master SOUT
Master SIN
PCS
t_CSC
t_CSC = PCS to SCK delay.
t_ASC = After SCK delay.
t_ASC
t_CSC
Figure 30-34. Example of Continuous Transfer (CPHA = 1, CONT = 1)
In Figure 30-34, the period length at the start of the next transfer is the sum of t_ASC and t_CSC; i.e., it does
not include a half-clock period. The default settings for these provide a total of four system clocks. In many
situations, t_ASC and t_CSC must be increased if a full half-clock period is required.
30-50
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor