PXN20RM Datasheet, PDF (414/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Semaphores
==
master_eq_cp{0,1}
=
=
=
wdata_eq_{unlock, cp[0-1]_lock}
gate0 gate1 gate2 gate3
0 aips_master
2
0 ips_wdata
31
ips_addr
decode
control
gate12 gate13 gate14 gate15
mux
cp0_semaphore_int cp1_semaphore_int
Figure 15-1. Semaphores Block Diagram
0
31
ips_rdata
IPS Bus
15.1.2 Features
The semaphores module implements hardware-enforced semaphores as a peripheral device and has these
major features:
• Support for 16 hardware-enforced gates in a dual-processor configuration
— Each hardware gate appears as a three-state, 2-bit state machine, with all 16 gates mapped as
an array of bytes
– Three-state implementation
if gate = 0b00, then state = unlocked
15-2
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor