PXN20RM Datasheet, PDF (311/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
timing diagram for this scenario, and Table 10-14 explains the events. The example is for software vector
mode, but except for the method of retrieving the vector and acknowledging the interrupt request to the
processor, hardware vector mode is identical.
Clock
B
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt Vector
0
Interrupt
Acknowledge
Write
INTC_CPR
Read
INTC_IACKR
Write
INTC_EOIR
C
E
H
INTVEC in
INTC_IACKR
108
208
D
F
I
PRI in
INTC_CPR
1
3
2
3
Last In / First Out
Entry in LIFO
0
3
0
Peripheral Interrupt
Request 100 _A
G
Peripheral Interrupt
Request 200
Figure 10-22. Raised Priority Preserved Timing Diagram
Table 10-14. Raised Priority Preserved Events
Event
Description
A Peripheral interrupt request 200 asserts during execution of ISR108 running at priority 1.
B Interrupt request to processor asserts. INTVEC in INTC_IACKR updates with vector for that peripheral interrupt
request.
C ISR108 writes to INTC_CPR to raise priority to 3 before accessing shared coherent data block.
D PRI in INTC_CPR now at 3, reflecting the write. This write, just before accessing data block, is the last instruction the
processor executes before being interrupted.
E Interrupt exception handler prolog acknowledges interrupt by reading INTC_IACKR.
F PRI of 3 pushed onto LIFO. PRI in INTC_CPR updates to 2, the priority of ISR208.
G ISR208 clears its flag bit, deasserting its peripheral interrupt request.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
10-43