PXN20RM Datasheet, PDF (933/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
Table 30-2. DSPI Memory Map (continued)
Offset from
DSPI_BASE
DSPI_A = 0xFFF9_0000
DSPI_B = 0xFFF9_4000
DSPI_C = 0xC3F9_0000
DSPI_D = 0xC3F9_4000
Register
Access Reset Value Section/Page
0x00D0
0x00D4–0x3FFF
DSPI_DSICR1—DSPI DSI TSB configuration register 1
Reserved
R/W 0x0000_0000 30.3.2.15/30-27
30.3.2 Register Descriptions
This section lists the DSPI registers in address order and describes the registers and their bit fields.
30.3.2.1 DSPI Module Configuration Register (DSPI_MCR)
The DSPI_MCR contains bits that configure various attributes associated with DSPI operation. The HALT
and MDIS bits can be changed at any time but only takes effect on the next frame boundary. Only the
HALT and MDIS bits in the DSPI_MCR may be changed while the DSPI is in the Running state.
Offset: DSPI_BASE + 0x0000
0
1
R
W
MSTR
CONT_
SCKE
Reset 0
0
2
3
DCONF
0
0
4
5
6
7
8
FRZ
MTFE
PCS
SE
ROOE
0
0
0
0
00
Access: User read/write
9
10
11
12
13
14
15
0 _{PCS PCS PCS PCS PCS PCS}
IS5 IS4 IS3 IS2 IS1 IS0
00
0
0
0
0
0
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
R0
W
MDIS
DIS_
TXF
DIS_ CLR_ CLR_
RXF TXF RXF
SMPL_PT
0
0
0
0
0
0
0
HALT
Reset 0
1
0
0
0
0
0
0 00 0
0
0
0
0
1
Figure 30-3. DSPI Module Configuration Register (DSPI_MCR)
Table 30-3. DSPI_MCR Field Descriptions
Field
Description
MSTR
Master/Slave Mode Select. The MSTR bit configures the DSPI for either Master Mode or Slave Mode.
0 DSPI is in Slave Mode.
1 DSPI is in Master Mode.
CONT_SCKE
Continuous SCK Enable. The CONT_SCKE bit enables the Serial Communication Clock (SCK) to run
continuously. See Section 30.4.9, Continuous Serial Communications Clock, for details.
0 Continuous SCK disabled.
1 Continuous SCK enabled.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
30-7