PXN20RM Datasheet, PDF (599/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
is busy (FEC_CRS asserts). Before transmitting, the controller waits for carrier sense to become inactive,
then determines if carrier sense stays inactive for 60 bit times. If so, the transmission begins after waiting
an additional 36 bit times (96 bit times after carrier sense originally became inactive). See Section
25.4.14.1, Transmission Errors, for more details.
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows
the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The
transmit FIFO stores at least the first 64 bytes of the transmit frame, so that they do not have to be retrieved
from system memory in case of a collision. This improves bus utilization and latency in case immediate
retransmission is necessary.
When all the frame data has been transmitted, the FCS (frame check sequence or 32-bit cyclic redundancy
check, CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the ABC bit is
set in the transmit frame control word, a bad CRC is appended to the frame data regardless of the TC bit
value. Following the transmission of the CRC, the Ethernet controller writes the frame status information
to the MIB block. Short frames are automatically padded by the transmit logic (if the TC bit in the transmit
buffer descriptor for the end of frame buffer = 1).
Both buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the settings in the
EIMR.
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If
the transmit frame length exceeds MAX_FL bytes, the BABT interrupt is asserted but the entire frame is
transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When the TCR[GTS]
is set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues
transmission until the current frame either finishes or terminates with a collision. After the transmitter has
stopped, the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes
transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
NOTE
At certain cases, the Fast Ethernet Controller (FEC) will transmit single
frames more than once. The FEC fetches the transmit buffer descriptors
(TxBDs) and the corresponding Tx data continuously until the Tx FIFO is
full. It does not determine whether the TxBD to be fetched is already being
processed internally (as a result of a wrap). As the FEC nears the end of the
transmission of one frame, it begins to DMA the data for the next frame. To
remain one BD ahead of the DMA, it also fetches the TxBD for the next
frame. The FEC may fetch a BD from memory that has already been
processed but not yet written back (it is read a second time with the R bit
still set). In this case, the data is fetched and transmitted again. Using at least
three TxBDs fixes this problem for large frames, but not for small frames.
To ensure correct operation for large or small frames, one of the following
must be true:
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
25-33