PXN20RM Datasheet, PDF (704/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0x0 R PPI NUF SYF SUF
FID
0x2
CYCCNT
PLDLEN
0x4
HDCRC
= not used
Figure 26-111. Frame Header Structure (Transmit Message Buffer for Key Slot)
Frame Header Access
The frame header is located in the FlexRay memory. To ensure data consistency, the application must
follow the write access scheme described below.
For receive message buffers, receive shadow buffers, and receive FIFOs, the application must not write to
the frame header field.
For transmit message buffers, the application must follow the write access restrictions given in
Table 26-84. This table shows the condition under which the application can write to the frame header
entries without corrupting the FlexRay message transmission.
Table 26-84. Frame Header Write Access Constraints (Transmit Message Buffer)
Field
FID
PPI,
PLDLEN,
HDCRC
Single Buffered
Static
Segment
Dynamic
Segment
MB_LCK
Double Buffered
Static Segment
Dynamic Segment
Commit Side
Transmit Side
POC:config or MB_DIS
POC:config or MB_DIS or
Commit Side
Transmit Side
MB_LCK
Frame Header Checks
As shown in Figure 26-110 and Figure 26-111 not all fields in the message buffer frame header are used
for transmission. Some fields in the message buffer frame header are ignored, some are used for
transmission, and some of them are checked for correct values. All checks that will be performed are
described below.
For message buffers assigned to the key slot, no checks will be performed.
The value of the FID field must be equal to the value of the corresponding Message Buffer Frame ID
Registers (MBFIDRn). If the controller detects a mismatch while transmitting the frame header, it will set
the frame ID error flag FID_EF in the CHI Error Flag Register (CHIERFR). The value of the FID field
will be ignored and replaced by the value provided in the Message Buffer Frame ID Registers (MBFIDRn).
For transmit message buffers assigned to the static segment, the PLDLEN value must be equal to the value
of the payload_length_static field in the Protocol Configuration Register 19 (PCR19). If this is not
fulfilled, the static payload length error flag SPL_EF in the CHI Error Flag Register (CHIERFR) is set
when the message buffer is under transmission. A syntactically and semantically correct frame is generated
with payload_length_static payload words and the payload length field in the transmitted frame header set
to payload_length_static.
26-90
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor