PXN20RM Datasheet, PDF (1175/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

36.6.2 Nexus3+ Block Diagram
Instruction
Snoop
Data
Snoop
Message
Queues
Memory Control
Nexus Development Interface (NDI)
I/O Logic
NPC
Control and
Arbitration
12
MDO[11:0]
MSEO0
MSEO1
MCKO
EVTO
EVTI
DMA
(Read/Write)
Registers
Control/Status
Registers
DMA Registers
OnCE Debug
Breakpoint/
Watchpoint
Control
TDI
TDO
TMS
TCLK
TRST
Nexus3 Module
Nexus1 Module (within core CPU)
Figure 36-13. e200z6 Nexus3 Functional Block Diagram
36.6.3 Nexus3+ Overview
Table 36-13 contains a set of terms and definitions associated with the Nexus3+ module.
Table 36-13. Terms and Definitions
Term
Description
IEEE-ISTO 5001
Consortium and standard for real-time embedded system design. World wide Web
documentation at http://www.ieee-isto.org/Nexus5001
Auxiliary Port
Refers to Nexus auxiliary port. Used as auxiliary port to the IEEE 1149.1 JTAG interface.
Branch Trace Messaging Visibility of addresses for taken branches and exceptions, and the number of sequential
(BTM)
instructions executed between each taken branch.
Client
A functional block on an embedded processor that requires development visibility and
controllability. Examples are a central processing unit (CPU) or an intelligent peripheral.
Data Read Message (DRM) External visibility of data reads to memory-mapped resources.
Data Write Message (DWM) External visibility of data writes to memory-mapped resources.
Data Trace Messaging (DTM) External visibility of how data flows through the embedded system. This may include DRM
and/or DWM.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-25