PXN20RM Datasheet, PDF (513/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

PIT Trigger #n+1
DMA Channel Multiplexer (DMA_MUX)
Peripheral Source #1
Peripheral Source #2
Peripheral Source #3
Always Disabled
Source #0
1
DMA Channel #n
n = 0 to 7
0
Peripheral Source #55
Always Enabled
Source #60
Always Enabled
Source #63
CHCONFIGn[TRIG]
CHCONFIGn[SOURCE]
Figure 23-3. DMA_MUX Channel 0–7 Block Diagram
The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on
the transmit side of certain peripherals, without the intervention of the processor. This trigger works by
gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in
Figure 23-4.
Peripheral Request
Trigger
DMA Request
Figure 23-4. DMA_MUX Channel Triggering: Normal Operation
After the DMA request has been serviced, the peripheral negates its request, effectively resetting the gating
mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means that
if a trigger is seen, but the peripheral is not requesting a transfer, that triggered is ignored. This situation
is illustrated in Figure 23-5.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
23-9