PXN20RM Datasheet, PDF (415/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Semaphores
if gate = 0b01, then state = locked by e200z6 (master ID = 0)
if gate = 0b10, then state = locked by e200z0 (master ID = 1)
– Uses the bus master ID number as a reference attribute plus the specified data patterns to
validate all write operations
– After it is locked, the gate must be unlocked by a write of zeroes from the locking processor
— Optionally enabled interrupt notification after a failed lock write provides a mechanism to
indicate the gate is unlocked
— Secure reset mechanisms are supported to clear the contents of individual semaphore gates or
notification logic, and clear_all capability
NOTE
Semaphore gates that are locked when entering sleep mode are cleared by
the internal reset generated when exiting sleep mode.
15.1.3 Modes of Operation
The semaphores module does not support any special modes of operation.
15.2 Signal Description
The semaphores module does not include any external signals.
15.3 Memory Map and Registers
This section provides a detailed description of all semaphores registers.
15.3.1 Module Memory Map
The semaphores programming model map is shown in Table 15-1. The address of each register is given as
an offset to the semaphore base address. Registers are listed in address order, identified by complete name
and mnemonic, and list the type of accesses allowed.
Table 15-1. Semaphores Memory Map
Offset from
SEMA4_BASE
(0xFFF1_0000)
Register
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
SEMA4_Gate00—Semaphores gate 0
SEMA4_Gate01—Semaphores gate 1
SEMA4_Gate02—Semaphores gate 2
SEMA4_Gate03—Semaphores gate 3
SEMA4_Gate04—Semaphores gate 4
SEMA4_Gate05—Semaphores gate 5
SEMA4_Gate06—Semaphores gate 6
Access Reset Value
Section/
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0x00
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0x00
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0x00
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R/W
0x00
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0x00
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R/W
0x00
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Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
15-3