PXN20RM Datasheet, PDF (281/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
Table 10-6. INTC_IACKR_PRC0 Field Descriptions
Field
Description
VTBA_PRC0
Vector Table Base Address for Processor 0 (Z6). VTBA_PRC0 can be the base address of a vector table of
addresses of ISRs for processor 0 (Z6). The VTBA_PRC0 only uses the leftmost 20 bits when the
VTES_PRC0 bit in INTC_MCR is asserted.
INTVEC_PRC0 Interrupt Vector for Processor 0 (Z6). INTVEC_PRC0 is the vector of the peripheral or software settable
interrupt request that caused the interrupt request to the processor. When the interrupt request to the
processor asserts, the INTVEC_PRC0 is updated, whether the INTC is in software or hardware vector mode.
The INTC_IACKR_PRCn provides a value that can be used to load the address of an ISR from a vector
table. The vector table can be composed of addresses of the ISRs specific to their respective interrupt
vectors.
In software vector mode, reading the INTC_IACKR_PRC0 acknowledges the INTC's interrupt request.
Refer to Section 10.1.3, Modes of Operation, for a detailed description of the effect on the interrupt request
to the processor. The reading also pushes the PRI value in the INTC current priority register
(INTC_CPR_PRCn) onto the LIFO and updates PRI in the INTC_CPR_PRCn with the priority of the
interrupt request. The side effect from the reads in software vector mode, that is, the effect on the interrupt
request to the processor, the current priority, and the LIFO, are the same regardless of the size of the read
Reading the INTC_IACKR_PRCn does not have side effects in hardware vector mode.
NOTE
The INTC_IACKR_PRCn must not be read speculatively while in software
vector mode. Therefore, for future compatibility, the TLB entry covering the
INTC_IACKR_PRCn must be configured to be guarded.
In software vector mode, the INTC_IACKR_PRCn must be read before
setting MSR[EE]. No synchronization instruction is needed after reading
the INTC_IACKR_PRCn and before setting MSR[EE].
However, the time for the processor to recognize the assertion or negation
of the external input to it is not defined by the book E architecture and can
be greater than 0. Therefore, insert instructions between the reading of the
INTC_IACKR_PRCn and the setting of MSR[EE] that consumes at least
two processor clock cycles. This length of time allows the interrupt request
negation to propagate through the processor before MSR[EE] is set.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
10-13