PXN20RM Datasheet, PDF (1030/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Data Bit Synchronization (Left Shifted Edges)
This kind of sample counter synchronization happens if the transmitter is faster than the receiver. The reset
behavior of the sample counter is shown in Figure 31-35. The sample counter reset condition is:
1. The data bit N – 1 is sampled as 1, and
2. The data bit N is sampled as 0, and
3. A falling edge consisting of three consecutive 1-samples and a following 0-sample is detected, and
4. The 0-sample of the falling edge is received at data bit N sample j, with 11  j  16.
If the condition is fulfilled, the sample counter is reset 16 RCLK cycles after the 0-sample of the falling
edge condition was received. The bit counter is increased by 1.
left shifted falling edge
sample counter reset
RXD
DATA FALLING
VOTING EDGE
DATABIT N-1
DATA
VOTING
DATABIT N
DATA
VOTING
DATABIT N+1
RCLK
RSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
wrap
reset
Figure 31-35. Data Bit Synchronization (Left Shifted Edges)
If the 0-sample of the falling edge condition is received at sample 9 or 10, no sample counter
synchronization is performed.
31.4.5.3.18 Stop Bit Verification
The reception of a valid stop bit is verified if at least two out of the sample RS8, RS9, and RS10 are
sampled high. If this is not that case, a framing error is detected. Noise is detected if not all of the samples
are of the same value. The results of the stop bit verification are summarized in Table 31-32.
Table 31-32. Stop Bit Verification
[RS8, RS9, RS10]
000
001
010
100
011
101
110
111
Stop Bit Verified
No
No
No
No
Yes
Yes
Yes
Yes
Framing Error Detected
Yes
Yes
Yes
Yes
No
No
No
No
Noise Detected
No
Yes
Yes
Yes
Yes
Yes
Yes
No
31-40
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor