PXN20RM Datasheet, PDF (117/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Resets
4.4.1 Reset Configuration Timing
The timing diagram in Figure 4-1 shows the sampling of the BOOTCFG (PK9) pin for a power-on reset.
The timing diagram is also valid for internal/external resets assuming V_DD and V_DD33 are within valid
operating ranges. The value of the BOOTCFG pin is latched 4 clock cycles before the negation of the
RESET pin and stored in the reset status register.
V_DD
POR
Internal
Reset
RESET
1000¹ clocks
(4 clock cycles)
BOOTCFG can be applied,
but not latched.
User drives
configuration pins
relative to RESET
1 _{If the CRP_RECPTR[FASTREC] is set, then the clock count is 16 for Sleep mode recovery.}
Figure 4-1. Reset Configuration Timing
BOOTCFG is latched.
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
4-5