PXN20RM Datasheet, PDF (159/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Clocks, Reset, and Power (CRP)
the 32 kHz OSC must be enabled before being selected. The 32 kHz OSC is selected to give a more
accurate wakeup than the 128 kHz IRC. (CNTEN must be disabled when the clock sources are switched.)
When the counter value for counter bits 10–21 match the 12-bit value in RTCVAL, then the RTCF interrupt
flag is set (after proper clock synchronization). If the RTCIE interrupt enable bit is set, the RTC interrupt
request is generated. The RTCF flag can be cleared by writing a 1 to RTCF. The RTCF supports interrupt
requests in the range of 1 second to 4096 seconds (> 1 hr) with a 1 second resolution.
NOTE
RTCVAL and APIVAL can be updated at any time.
If there is a match while in sleep mode, and the CRP_PSCR[RTCWKEN] bit is set, then the RTC first
generates a wakeup request to force a wakeup to run mode, then sets the RTCF flag. The RTC wakeup
signal is captured in the CRP_PSCR[WKRTCF] flag bit.
A rollover wakeup and/or interrupt can be generated when the RTC transitions from a count of
0xFFFF_FFFF to 0x0000_0000. The rollover flag is enabled by setting the CRP_RTCC[ROVREN] bit.
An RTC counter rollover with this bit and the CRP_PSCR[RTCOVRWKEN] bit set causes a wakeup from
sleep mode. The rollover wakeup flag is captured in the CRP_PSCR[WKRLLOVRF] bit. An interrupt
request is generated for an RTC counter rollover when both the CRP_RTCC[ROVREN] and
CRP_RTCC[RTCIE] bits are set.
Setting APIEN enables the autonomous interrupt function. The 10 bit APIVAL selects the time interval for
triggering an interrupt and/or wakeup event. Since the RTC is a free-running counter, the APIVAL is added
to the current count to calculate an offset. When the counter reaches the offset count, a interrupt and/or
wakeup request is generated. Then the offset value is recalculated and again retriggers a new request when
the new value is reached. APIVAL (and RTCVAL) can be updated at any time. When a compare is reached,
the APIF interrupt flag is set (after proper clock synchronization). If the APIIE interrupt enable bit is set,
then the API interrupt request is generated. The APIF flag can be cleared by writing a 1 to APIF. If there
is a match while in sleep mode, and the CRP_PSCR[APIWKEN] bit is set, then the API first generates a
wakeup request to force a wakeup to run mode, then sets the APIF flag. The API wakeup flag is captured
in the CRP_PSCR[WKAPIF] bit.
If the CRP_RTCC[FRZEN] bit is set, the RTC counter is frozen during debug mode.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
6-27