PXN20RM Datasheet, PDF (1034/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Break
Synch Identifier Data 1
Data 2
Data N
CRC1
Figure 31-39. CRC Enhanced LIN Frame Format
The CRC Enhanced LIN frames are not part of the LIN standard.
CRC2 Checksum
31.4.6.3 LIN TX Frame Generation
The eSCI module supports two modes of LIN TX Frame generation. In the application controlled mode,
the application provides the required frame configuration and frame data by subsequent write accesses to
the eSCI LIN Transmit Register (eSCI_LTR). In the DMA generation mode, the DMA controller provides
the required frame configuration and frame data in response to DMA requests generated by the eSCI
module.
31.4.6.3.1 CPU Controlled LIN TX Frame Generation
In this mode, the application initiates the generation of a LIN TX Frame and provides the data to be
transmitted by a sequence of subsequent CPU write accesses to the eSCI LIN Transmit Register
(eSCI_LTR). When the eSCI module has processed the data written into the eSCI LIN Transmit Register
(eSCI_LTR), the TXRDY interrupt flag in the eSCI Interrupt Flag and Status Register 2 (eSCI_IFSR2) is
set.
The application should clear the TXRDY interrupt flag before writing data into the eSCI LIN Transmit
Register (eSCI_LTR) because the eSCI module sets the TXRDY one clock cycle after the write access.
The first data written to the eSCI LIN Transmit Register (eSCI_LTR) provides the Identifier and Identifier
Parity fields. The second data written defines the number of data bytes to be transmitted. The third data
written defines the CRC and checksum generation. The TD bit has to be set to 1 in order to invoke the LIN
TX frame generation. The value of the TO field is ignored by the eSCI module for LIN TX frames.
After the third data is written, the generation of a LIN TX frame is started. First, a break field is transmitted,
then the synch field and the protected identifier field.
All subsequent write accesses to the eSCI LIN Transmit Register (eSCI_LTR) provide data bytes to be
transmitted via the LIN bus. A data byte field is transmitted as soon as data are available. After the last
data byte (defined by the value written to the LEN field) is sent, the configured CRC and checksum fields
are sent out.
After the transmission of the checksum field of the LIN TX frame, the write access counter for the eSCI
LIN Transmit Register (eSCI_LTR) is reset and the FRC interrupt flag in the eSCI Interrupt Flag and Status
Register 2 (eSCI_IFSR2) is set.
31-44
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor