PXN20RM Datasheet, PDF (1131/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
NOTE
If the higher threshold for the analog watchdog is programmed lower than
the lower threshold and the converted value is lesser than the lower
threshold then the WDGnL interrupt for the low threshold violation is set,
else if the converted value is greater than the lower threshold (consequently
also greater than the higher threshold) then the interrupt WDGnH for high
threshold violation is set. Thus the user should take care of avoiding that
situation as it could lead to misinterpretation of the watchdog interrupts.
34.4.5.1 Analog Watchdog Pulse Width Modulation Bus
For each input channel, an output bus is used to signal outside the result of the comparison generating
modulated pulse waveforms based on the converted analog values received by the analog watchdogs:
• If the converted data value is lower than the lower threshold, then the output pin (and THROP bit
in TRCn register) is forced high.
• If the converted voltage is higher than the higher threshold, then the output pin (and THROP bit in
TRCn register) is forced low.
• If the converted voltage lies between the upper and the lower threshold guard window, then the
output pin (and THROP bit in TRCn register) keeps its logic value.
The logic level of the output pin can be programmed by software. In fact, the user can decide to keep the
behavior described or to invert the output logic level by setting the THRINV bit in the TRCn register.
The values set on the ad_awpwm bus remain same in case the alternate watchdog thresholds are employed
by enabling the corresponding bit of the alternate watchdog input bus.
An example of the operation is shown in Table 34-44.
Table 34-44. Example for ad_awpwm_o Operation
Converted data
watchdog(n)
0x0155
0x0055
0x0155
0x0055
Upper Threshold
watchdog(n)
0x0055
0x01FF
0x0055
0x01FF
Lower Threshold
watchdog(n)
0x0000
0x0088
0x0000
0x0088
THRINV
watchdog(n)
0
0
1
1
AD_AWPWM(n)
0
1
1
0
34.4.6 DMA Functionality
A Direct Memory Access (DMA) request can be programmed after the conversion of every channel by
setting the respective masking bit in DMARn registers. The DMA masking registers must be programmed
before starting any conversion.
DMA interface signals timings are described in Figure 34-51.
DMA transfers can be enabled by setting the DMAE[DMAEN] bit. When DMAE[DCLR] is set then the
DMA request is cleared on the reading of the register for which DMA transfer has been enabled.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
34-51