PXN20RM Datasheet, PDF (1141/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
35.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port
The JTAGC uses the IEEE 1149.1-2001 TAP for accessing registers. This port can be shared with other
TAP controllers on the MCU. Ownership of the port is determined by the value of the JCOMP signal and
the currently loaded instruction. For more detail on TAP sharing via JTAGC instructions refer to
Section 35.4.4.2, ACCESS_AUX_TAP_x Instructions.
Data is shifted between TDI and TDO though the selected register starting with the least significant bit, as
illustrated in Figure 35-5. This applies for the instruction register, test data registers, and the bypass
register.
MSB
LSB
TDI
Selected Register
TDO
Figure 35-5. Shifting Data Through a Register
35.4.3 TAP Controller State Machine
The TAP controller is a synchronous state machine that interprets the sequence of logical values on the
TMS pin. Figure 35-6 shows the machine’s states. The value shown next to each state is the value of the
TMS signal sampled on the rising edge of the TCK signal. As Figure 35-6 shows, holding TMS at logic 1
while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the
test-logic-reset state.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
35-7