PXN20RM Datasheet, PDF (1171/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
TEST-LOGIC-RESET = 1
NEXUS-ENABLE = 0
IDLE
NEXUS-ENABLE = 1
REG_SELECT
NEXUS-ENABLE = 1 && UPDATE-DR = 1
UPDATE-IR = 1
UPDATE-DR = 1
DATA_ACCESS
Figure 36-11. NEXUS Controller State Machine
Table 36-11. Loading NEXUS-ENABLE Instruction
Clock TDI
0
—
1
—
2
—
3
—
4
—
5-7
0
8
0
9
—
10
—
TMS
0
1
1
0
0
0
1
1
0
IEEE 1149.1 State
RUN-TEST/IDLE
SELECT-DR-SCAN
SELECT-IR-SCAN
CAPTURE-IR
SHIFT-IR
3 TCKS in SHIFT-IR
EXIT1-IR
UPDATE-IR
RUN-TEST/IDLE
Nexus State
Description
IDLE
IEEE 1149.1-2001 TAP controller in idle state
IDLE
Transitional state
IDLE
Transitional state
IDLE
IDLE
IDLE
Internal shifter loaded with current instruction
TDO becomes active, and the IEEE 1149.1-2001
shifter is ready. Shift in all but the last bit of the
NEXUS_ENABLE instruction.
IDLE
Last bit of instruction shifted in
IDLE
NEXUS-ENABLE loaded into instruction register
REG_SELECT Ready to be read/write Nexus registers
Selecting a Nexus Client Register
When the NEXUS-ENABLE instruction is decoded by the TAP controller, the input port allows
development tool access to all Nexus registers. Each register has a 7-bit address index.
All register access is performed via the SELECT-DR-SCAN path of the IEEE 1149.1–2001 TAP
controller state machine. The Nexus controller defaults to the REG_SELECT state when enabled.
Accessing a register requires two passes through the SELECT-DR-SCAN path: one pass to select the
register and the second pass to read/write the register.
The first pass through the SELECT-DR-SCAN path is used to enter an 8-bit Nexus command consisting
of a read/write control bit in the LSB followed by a 7-bit register address index, as illustrated in
Figure 36-12. The read/write control bit is set to 1 for writes and 0 for reads.
Figure 36-12. IEEE 1149.1 Controller Command Input
MSB
7-bit register index
LSB
R/W
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-21