PXN20RM Datasheet, PDF (365/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Chapter 13
e200z6 Core (Z6)
13.1 Introduction
The core complex of the PXN20 device consists of the following:
• e200z650n3e core described in this chapter
• 32 KB unified cache memory
• 32-entry memory management unit (MMU)
• Nexus class 3 block
• Bus interface unit (BIU)
The e200z6 core is the central processing unit (CPU) in the device. The core is part of the family of CPU
cores that implement versions built on the Power Architecture embedded category.
The core is 100% user mode compatible with the original Power PC user instruction set architecture
(UISA). However, in the Power Architecture definition, the original floating-point resources (used by a
SIMD design supporting single-precision vector and single-precision scalar operations) are provided that
share the GPRs defined for integer instructions.
Throughout this book, the e200z650n3e core may also be referred to as the Z6 or the e200z6. In the context
of the PXN20 device, these terms are interchangeable. Refer to the e200z6 PowerPC^TM Core Reference
Manual for more information on the e200z6 core.
The e200z0 core, used on this device as an I/O processor, is described in Chapter 14, e200z0 Core (Z0).
13.1.1 Block Diagram
Figure 13-1 shows a block diagram of the e200z6 core complex.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
13-1