PXN20RM Datasheet, PDF (568/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
PBRIDGE_B
System Bus Crossbar Switch (XBAR)
Slave Interface
FEC Block
Bus
Controller
Descriptor
Controller
(RISC +
microcode)
MII
MDO
MDI
MDEN
CSR
RAM
FIFO
Controller
RAM I/F
DMA
FEC Bus
MIB
Counters
Transmit
Receive
I/O
PAD
FEC_MDIO FEC_MDC
FEC_TX_EN
FEC_TXD[3:0]
FEC_TX_ER
FEC_TX_CLK FEC_RX_CLK
FEC_CRS
FEC_COL
FEC_RX_DV
FEC_RXD[3:0]
FEC_RX_ER
MII/7-WIRE DATA
OPTION
Figure 25-1. FEC Block Diagram
25.1.2 Overview
The Ethernet media access controller (MAC) is designed to support both 10 and 100 Mbps Ethernet/IEEE
802.3 networks. An external transceiver interface and transceiver function are required to complete the
interface to the media. The FEC supports three different standard MAC-PHY (physical) interfaces for
connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10
Mbps-only 7-wire interface, which uses a subset of the MII signals.
The descriptor controller is a RISC-based controller that provides the following functions in the FEC:
25-2
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor