PXN20RM Datasheet, PDF (243/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
maintain their previous state. This is accomplished by writing a 16-bit masked value coherently with an
update value contained in a 16-bit output field, and only updating those bits in the output register for which
the corresponding mask bit is set.
Offset: SIU_BASE + 0x0D14
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK}
W ^{15 14 13 12 11 10 9}
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
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30
31
R _{DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA}
W ^{15 14 13 12 11 10 9}
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-59. Masked Serial GPO Register for DSPI_C Low (SIU_DSPICL)
Table 8-38. SIU_DSPICL Field Descriptions
Field
Description
MASKn
DATAn
Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_C.
0 The previous value defined by GPO for DSPI_C is maintained.
1 The corresponding GPO for DSPI_C is written with the value defined by the DATAn field.
Pin Data Out. This bit stores the data to be driven out on the GPO for DSPI_C output controlled by this register.
0 Logic low value is driven for the corresponding GPO for DSPI_C when this output is selected in the DSPI
serialization module.
1 Logic high value is driven for the corresponding GPO for DSPI_C when this output is selected in the DSPI
serialization module.
8.3.2.52 Masked Serial GPO Register for DSPI_D High (SIU_DSPIDH)
The SIU_DSPIDH register allows any combination of bits in the top half of the 32-bit serialized data frame
from DSPI_D to be updated with a single 32-bit write operation, while allowing other bits to maintain their
previous state. This is accomplished by writing a 16-bit masked value coherently with an update value
contained in a 16-bit output field, and only updating those bits in the output register for which the
corresponding mask bit is set.
Offset: SIU_BASE + 0x0D18
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK}
W ^{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA}
W ^{31 30 29 28 27 26 25 24 23 222 21 20 19 18 17 16}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-60. Masked Serial GPO Register for DSPI_D High (SIU_DSPIDH)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-61