PXN20RM Datasheet, PDF (418/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Semaphores
Field
INEn
Table 15-3. SEMA4_CP{0,1}NTF Field Descriptions
Description
Interrupt Request Notification Enable n. This field is a bitmap to enable the generation of an interrupt notification
from a failed attempt to lock gate n.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
15.3.2.3 Semaphores Processor n IRQ Notification (SEMA4_CP{0,1}NTF)
The notification interrupt is generated via a unique finite state machine, one per hardware gate. This
machine operates in the following manner:
• When an attempted lock fails, the FSM enters a first state where it waits until the gate is unlocked.
• After it is unlocked, the FSM enters a second state where it generates an interrupt request to the
failed lock processor.
• When the failed lock processor succeeds in locking the gate, the IRQ is automatically negated and
the FSM returns to the idle state. However, if the other processor locks the gate again, the FSM
returns to the first state, negates the interrupt request, and waits for the gate to be unlocked again.
The notification interrupt request is implemented in a 3-bit, five-state machine, where two specific states
are encoded and program-visible as SEMA4_CP0NTF[GNn] and SEMA4_CP1NTF[GNn].
Offset: SEMA4_BASE + 0x0080 (SEMA4_CP0NTF)
SEMA4_BASE + 0x0088 (SEMA4_CP1NTF)
Access: User read-only
0
R GN0
W
Reset 0
1
GN1
0
2
GN2
0
3
GN3
0
4
GN4
0
5
GN5
0
6
GN6
0
7
GN7
0
8
GN8
0
9
10
11
12
13
14
15
GN9 GN10 GN11 GN12 GN13 GN14 GN15
0
0
0
0
0
0
0
Figure 15-4. Semaphores Processor n IRQ Notification (SEMA4_CP{0,1}NTF)
Table 15-4. SEMA4_CP{0,1}NTF Field Descriptions
Field
Description
GNn
Gate n Notification. This read-only field is a bitmap of the interrupt request notification from a failed attempt to lock
gate n.
0 No notification interrupt generated.
1 Notification interrupt generated.
15.3.2.4 Semaphores (Secure) Reset Gate n (SEMA4_RSTGT)
Although the intent of the hardware gate implementation specifies a protocol where the locking processor
must unlock the gate, it is recognized that system operation may require a reset function to re-initialize the
state of any gate(s) without requiring a system-level reset.
To support this special gate reset requirement, the semaphores module implements a secure reset
mechanism which allows a hardware gate (or all the gates) to be initialized by following a specific
dual-write access pattern. Using a technique similar to that required for the servicing of a software
15-6
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor