PXN20RM Datasheet, PDF (860/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
MODE[4] = 1, the counter changes direction at the A1 match and counts down until it reaches the value
one. After it has reached one, it is set to count in up direction again. Register B1 is set to one at mode
entering and cannot be changed while this mode is selected. B1 register is used to generate a match to set
the internal counter in up-count direction if up/down mode is selected.
The MCB mode counts between one and A1 register value. Only values greater than 0x00_0001 are
allowed to be written at A1 register. Loading values other than those leads to unpredictable results. The
counter cycle period is equal to A1 value in up counter mode. If in up/down counter mode the period is
defined by the expression: (2*A1) – 2.
Figure 28-35 shows the counter cycle for several A1 values. Register A1 is loaded with A2 register value
at the cycle boundary. Any value written to A2 register within cycle (n) is updated to A1 at the next cycle
boundary and therefore is used on cycle (n + 1). The cycle boundary between cycle (n) and cycle (n + 1)
is defined as the first system clock cycle of cycle (n + 1). The flags are generated as soon as A1 match had
occurred.
EMIOS_CCNTR[n]
0x000007
0x000006
0x000005
Write to A2
A1 Match
Write to A2
A1 Match
A1 Match
0x000001
FLAG Set Event
A2 Value
A1 Value 0x000006
0x000005
0x000007
0x000005
0x000007
Figure 28-35. Modulus Counter Buffered (MCB) Up Count Mode
Time
0x000007
Figure 28-36 shows the MCB in up/down counter mode. Register A1 is updated at the cycle boundary. If
A2 is written in cycle (n), this new value is used in cycle (n + 1) for A1 match.
Flags are generated at A1 match only if MODE[5] is 0. If MODE[5] is set to 1, flags are also generated at
the cycle boundary.
28-38
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor