PXN20RM Datasheet, PDF (251/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
combined overrun interrupt request is used in the device, and the individual overrun requests are not
connected.
Each IRQ pin has a programmable filter for rejecting glitches on the IRQ signals. The filter length for the
IRQ pins is specified in the external IRQ digital filter register (SIU_IDFR).
External
IRQ pins or
internal
sources
PC6
PC5
SIU
IMUX
••
••
SIU_EISR
EIF0
EIF1
EIF2
EIF3
EIF4
••
••
EIF15
NMI1
NMI0
SIU_OSR
OVF0
OVF1
•_••
•••
OVF15
SIU_DIRSR
DIRS0
DIRS1
DIRS0
DIRS1
DIRS0
DIRS1
EIF4–EIF15
Overrun
request
DMA
request
eDMA
Interrupt
controller
Critical
interrupt
Secondary
CPU
Primary
CPU
Figure 8-70. SIU DMA/Interrupt Request Diagram
8.4.4 GPIO Operation
All GPIO functionality is provided by the SIU. Each pin that has GPIO functionality has an associated Pin
Configuration Register in the SIU where the GPIO function is selected for the pin. In addition, each pin
with GPIO functionality has an input data register (SIU_GPDIn) and an output data register
(SIU_GPDOn). The SIU also implements several parallel GPIO registers (SIU_PGPDOn and
SIU_PGPDIn) that can be used to access as many as 32 GPIO bits in single- and word-sized accesses. The
values read/written to these parallel register is coherent with the data read/written to the SIU_GPDOn and
SIU_GPDIn registers.
8.4.5 Internal Multiplexing
The IMUX Select Registers (SIU_ISELn) provide selection of the input source for the ADC external
trigger inputs and the SIU external interrupts.
8.4.5.1 ADC External Trigger Input Multiplexing
The two ADC external trigger inputs (start of conversion and injected trigger) can be connected to four
different external pins or to PIT2. The input source for each ADC external trigger is individually specified
in the IMUX Select Register 4 (SIU_ISEL4). Figure Figure 8-71 gives an example of the multiplexing of
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-69