PXN20RM Datasheet, PDF (956/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
In SPI configuration, master mode transfer attributes are controlled by the SPI command in the current TX
FIFO entry. The CTAS field in the SPI command selects which of the eight DSPI_CTARn registers are
used to set the transfer attributes. Transfer attribute control is on a frame by frame basis. See
Section 30.4.3, Serial Peripheral Interface (SPI) Configuration, for more details.
In DSI configuration, master mode transfer attributes are controlled by the DSPI DSI Configuration
Register (DSPI_DSICR). A detailed description of the DSPI_DSCIR is located in Section 30.3.2.10, DSPI
DSI Configuration Register (DSPI_DSICR). The DSISCTAS field in the DSPI_DSICR selects which of
the DSPI_CTARn registers are used to set the transfer attributes. Transfer attributes are set up during
initialization and should not be changed between frames. See Section 30.4.4, Deserial Serial Interface
(DSI) Configuration, for more details.
The CSI configuration is only available in master mode. In CSI configuration, the DSI data is transferred
using DSI configuration transfer attributes and SPI data is transferred using the SPI configuration transfer
attributes. In order for the bus slave to distinguish between DSI and SPI frames, the transfer attributes for
the two types of frames must utilize different peripheral chip select signals. See Section 30.4.5, Combined
Serial Interface (CSI) Configuration, for details.
30.4.1.2 Slave Mode
In slave mode, the DSPI responds to transfers initiated by a SPI master. The DSPI operates as bus slave
when the MSTR bit in the DSPI_MCR register is negated. The DSPI slave is selected by a bus master by
having the slave’s SS asserted. In slave mode, the SCK is provided by the bus master. All transfer attributes
are controlled by the bus master. However, clock polarity, clock phase, and numbers of bits to transfer must
still be configured in the DSPI slave for proper communications.
The SPI and DSI configurations are valid in slave mode. In SPI slave mode, the slave transfer attributes
are set in the DSPI_CTAR0. In DSI slave mode, the slave transfer attributes are set in the DSPI_CTAR1.
In both SPI and DSI configurations, the DSPI in slave mode transfers data MSB first. The LSBFE field of
the associated CTAR is ignored.
30.4.1.3 Module Disable Mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI can be stopped while in module disable mode.The DSPI enters the module disable mode
when the MDIS bit in DSPI_MCR is set. Logic external to the DSPI is needed to implement the module
disable mode. See Section 30.4.13, Power Saving Features, for more details on the module disable mode.
30.4.1.4 Halt Mode
When the appropriate bit in the SIU_HLT0 register is set, a request to enter halt mode is sent to the DSPI.
The DSPI does not acknowledge the request to enter halt mode until it has reached a frame boundary.
When the DSPI has reached a frame boundary, it halts all operations and indicates that it is ready to have
its clocks shut off. The DSPI exits halt mode and resumes normal operation once the clocks are turned on.
Serial communications or register accesses made while in halt mode are ignored even if the clocks have
not been shut off yet. See Section 30.4.13, Power Saving Features, for more details on the halt mode.
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor