PXN20RM Datasheet, PDF (247/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Table 8-44. SIU_DSPIBHLB Field Descriptions
Field
Description
DSPIBHn Data Path Enable for DSPI_B High.
0 Data path disabled to DSPI_B High.
1 Data path enabled to DSPI_B High.
DSPIBLn Data Path Enable for DSPI_B Low.
0 Data path disabled to DSPI_B Low.
1 Data path enabled to DSPI_B Low.
8.3.2.58 eMIOS Select Register for DSPI_C (SIU_EMIOSC)
The SIU_EMIOSC register selects the output serialized source for the DSPI_C channel.
Offset: SIU_BASE + 0x0D64
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS}
W ³¹
30
29
28
27
26
25
24
23 22 21 20 19 18 17
16
Reset 0
0
0
0
0
0
0
0
0000000
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS}
W ¹⁵
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0000000
0
Figure 8-66. eMIOS Select Register for DSPI_C (SIU_EMIOSC)
Table 8-45. SIU_EMIOSC Field Descriptions
Field
Description
EMIOSn
eMIOS Channel Enable.
0 This eMIOS channel is not enabled.
1 This eMIOS channel is enabled.
8.3.2.59 SIU_DSPICH/L Select Register for DSPI_C (SIU_DSPICHLC)
The SIU_DSPICHLC register enables the data path from the Masked Serial GPO register for DSPI_C to
the equivalent bit position in the DSPI_C channel frame.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-65