PXN20RM Datasheet, PDF (796/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Offset: 0x004C (CNBCR0)
0x005C (CNBCR1)
0x006C (CNBCR2)
0x007C (CNBCR3)
0x008C (CNBCR4)
0x009C (CNBCR5)
0x00AC (CNBCR6)
0x00BC (CNBCR7)
0x00CC (CNBCR8)
0x00DC (CNBCR9)
0x00EC (CNBCR10)
0x00FC (CNBCR11)
0x010C (CNBCR12)
0x011C (CNBCR13)
0x012C (CNBCR14)
0x013C (CNBCR15)
0
1
2
3
4
5
6
7
8
9
10
11
R
BSA[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
12
13
14
15
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
BEA[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-15. Channel n Next Buffer Configuration Register
Table 27-21. Channel n Next Buffer Configuration Register Field Descriptions
Field
Description
BSA
[15:0]
Buffer Start Address. The BSA field defines a 16-bit address pointer, which identifies the lower half of the beginning
address of the Next Buffer in system memory. Once system software detects CSCRn[RDY]has been cleared by
hardware (for ping-pong buffering), the beginning address of the Next Buffer may be loaded into BSA[15:2]. System
software should then set CSCRn[RDY]. Once processing of the Current Buffer for the logical channel is complete,
the BSA[15:2] field is loaded into the CCBCRn[BCA[15:2]] field and processing of the next buffer can begin. This
Next Buffer address pointer must always be quadlet aligned (e.g. BSA[1:0] must be written as 2’b00).
BEA
[15:0]
The upper half of the beginning address of the Next Buffer in system memory is defined by SBCR[SRBA],
ABCA[ARBA], CBCR[CRBA], or IBCR[IRBA] when CECRn[TR] is clear; SBCR[STBA], ABCA[ATBA], CBCR[CTBA,
or IBCR[ITBA] when CECRn[TR] is set, depending on the value of CECRn[CT[1:0]].
Buffer End Address. The BEA field defines a 16-bit address pointer, which identifies the lower half of the ending
address of the Next Buffer in system memory. Once system software detects CSCRn[RDY] has been cleared by
hardware (for ping-pong buffering), the ending address of the Next Buffer may be loaded into BEA[15:2]. System
software should then set CSCRn[RDY]. Once processing of the Current Buffer for the logical channel is complete,
the BEA[15:2] field is loaded into the CCBCRn[BFA[15:2]] field and processing of the next buffer can begin. The
BEA[15:2] bits are loaded into CCBCRn[BFA[15:2]] when the Current Buffer is finished being processed. This Next
Buffer address pointer, except when associated with isochronous channels, should always be quadlet aligned (e.g.
BEA[1:0] defaults to 2’b00).
The upper half of the ending address of the Next Buffer in system memory is defined by SBCR[SRBA], ABCA[ARBA],
CBCR[CRBA], or IBCR[IRBA] when CECRn[TR] is clear; SBCR[STBA], ABCA[ATBA], CBCR[CTBA, or IBCR[ITBA]
when CECRn[TR] is set, depending on the value of CECRn[CT[1:0]].
27.3.2.15 Local Channel n Buffer Configuration Register
The Local Channel n Buffer Configuration Register (LCBCRn) allows software to optimize use of the
local buffer RAM for local channel buffering. This register should only be written by software while the
logical channel is disabled (e.g. CECR3[CE] clear disables Channel 3; therefore software may write
27-24
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor