PXN20RM Datasheet, PDF (1002/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Field
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
BERR
TACT
RACT
Table 31-7. eSCI_IFSR1 Field Descriptions
Description
Transmit Data Register Empty Interrupt Flag. This interrupt flag is set when the content of the SCI Data Register
(eSCI_SDR) is transferred into the internal shift register.
Note: This flag is set in SCI mode only.
Transmit Complete Interrupt Flag. This interrupt flag is set when a frame, break or idle character transmission
has been completed and no data were written into SCI Data Register (eSCI_SDR) after the last setting of the
TDRE flag and the SBK bit in Control Register 1 (eSCI_CR1) is 0.
This flag is set in LIN mode if the preamble was transmitted after enabling the transmitter.
Receive Data Register Full Interrupt Flag. This interrupt flag is set when the payload data of a received frame is
transferred into the SCI Data Register (eSCI_SDR).
Note: This flag is set in SCI mode only.
Idle Line Flag. This flag is set when an idle character was detected and the receiver is not in the wakeup state.
Note: This flag is set in SCI mode only.
Overrun Flag. This flag is set when an overrun was detected as described in Section 31.4.5.3.11, Receiver
Overrun.
Note: This flag is set in SCI mode only.
Noise Interrupt Flag. This flag is set when the payload data of a received frame was transferred into the SCI Data
Register (eSCI_SDR) or LIN Receive Register (eSCI_LRR) and the receiver has detected noise during the
reception of that frame, as described in Section 31.4.5.3.13, Bit Sampling.
Framing Error Interrupt Flag. This interrupt flag is set when the payload data of a received frame was transferred
into the SCI Data Register (eSCI_SDR) or LIN Receive Register (eSCI_LRR) and the receiver has detected a
framing error during the reception of that frame, as described in Section 31.4.5.3.18, Stop Bit Verification.
Parity Error Interrupt Flag. This interrupt flag is set when the payload data of a received frame was transferred
into the SCI Data Register (eSCI_SDR) and the receiver has detected a parity error for the character, as
described in Section 31.4.5.4, Reception Error Reporting.
Note: This flag is set in SCI mode only.
Bit Error Flag. This flag is set when a bit error was detected as described in Section 31.4.6.5.3, Standard Bit Error
Detection.
Note: This flag is set in LIN mode only.
Transmitter Active. The status bit is set as long as the transmission of a frame or special character is ongoing.
0 No transmission in progress.
1 Transmission in progress.
Receiver Active. The bit is set 3 receiver clock (RCLK) cycles after the successful qualification of a start bit. This
bit is cleared when an idle character is detected.
0 No reception in progress.
1 Reception in progress.
31.3.2.6 eSCI Interrupt Flag and Status Register 2 (eSCI_IFSR2)
This register provides interrupt flags that indicate the occurrence of LIN related events. The related
interrupt enable bits are located in eSCI LIN Control Register 1 (eSCI_LCR1) and eSCI LIN Control
Register 2 (eSCI_LCR2). All interrupt flags in this register are set in LIN mode only.
31-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor